MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 480

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.6.3.2
The USB status register indicates various states of each module and any pending interrupts. This register
does not indicate status resulting from a transaction on the serial bus. The software clears certain bits in
this register by writing a 1 to them (indicated by a W1C in the bit’s W cell in the figure).
24-18
Address MBAR2 0x744
Reset
Reset
31–16
Field
HCH
11–9
RCL
AS
PS
15
14
13
12
W
W
R
R
AS
31
15
0
0
USB Status Register (USBSTS)
Reserved.
Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous Schedule. The
controller is not required to immediately disable or enable the Asynchronous Schedule when the software
transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or
disabled (0). Used only in host mode.
1 Enabled.
0 Disabled.
Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule. The controller is not
required to immediately disable or enable the Periodic Schedule when the software transitions the Periodic
Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same
value, the Periodic Schedule
is either enabled (1) or disabled (0). Used only in host mode.
1 Enabled.
0 Disabled.
Reclamation. This is a status bit used to detect an empty asynchronous schedule. Used only in host mode.
1 Empty asynchronous schedule.
0 Non-empty asynchronous schedule.
HCHaIted. This bit is a zero whenever the Run/Stop bit is a one. The controller sets this bit to one after it has
stopped executing because of the Run/Stop bit being set to 0, either by the software or by the Host Controller
hardware (for example, internal error). Used only in host mode.
1 Halted.
0 Running.
Reserved.
PS
30
14
0
0
Table 24-16. USB Status Register (USBSTS) Register Field Descriptions
RCL
29
13
0
0
Figure 24-15. USB Status Register (USBSTS) Register
HCH
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
W1C W1C W1C W1C W1C W1C W1C W1C W1C
SLI
24
0
0
8
Description
SRI
23
0
1
7
URI
22
0
0
6
AAI
21
0
0
5
SEI
20
0
0
4
FRI
19
0
0
3
Freescale Semiconductor
Access: User read/write
PCI
18
0
0
2
UEI
17
0
0
1
UI
16
0
0
0