MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 358

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

I
18.6.3
Transmission or reception of a byte will set the data transferring bit (ICF) to 1, which indicates one byte
communication is finished. The interrupt bit (IIF) is also set. An interrupt will be generated if the interrupt
function is enabled during initialization by setting the IIEN bit. Software must clear the IIF bit in the
interrupt routine first. The ICF bit will be cleared by reading from the I
receive mode or writing to MBDR in transmit mode.
Software can service the I
disabled. Polling should monitor the IIF bit rather than the ICF bit because that operation is different when
arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master will always be in transmit mode. For
example, the address is transmitted. If master receive mode is required, indicated by MBDR[R/W], then
the MTX bit should be toggled.
During slave-mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the MTX bit is programmed accordingly. For slave-mode data
cycles (IAAS=0), the SRW bit is not valid. The MTX bit in the control register should be read to determine
the direction of the current transfer.
The following is an example of a software response by a “master transmitter’' in the interrupt routine (see
Figure
MBSR
END
TRANSMIT MOVE.B
18.6.4
A data transfer ends with a STOP signal generated by the “master’' device. A master transmitter can
generate a STOP signal after all the data has been transmitted. The following code is an example showing
how a master transmitter generates a stop condition.
MASTX
18-14
2
C Modules
18-9).
LEA.L
BCLR.B
MOVE.B
BTST.B
BEQ.S
MOVE.B
BTST.B
BEQ.S
MOVE.B
BTST.B
BNE.B
MOVE.B
MOVE.B
BTST.B
BNE.B
MOVE.B
BEQ.S
MOVE.B
MOVE.B
MOVE.B
SUBQ.L
Post-Transfer Software Response
Generation of STOP
MBSR,-(A7)
#1,(A7)+
MBCR,-(A7)
#5,(A7)+
SLAVE
MBCR,-(A7)
#4,(A7)+
RECEIVE
MBSR,-(A7)
#0,(A7)+
DATABUF,-(A7)
(A7)+, MBDR)
MBSR, -(A7)
#0,(A7)+
END
TXCNT,D0
END
DATABUF,-(A7)
(A7)+,MBDR
TXCNT,D0
#1,D0
2
C I/O in the main program by monitoring the IIF bit if the interrupt function is
;If no ACK, end of transmission
MCF5253 Reference Manual, Rev. 1
;Load effective address
;Clear the IIF flag
;Push the address on stack,
;check the MSTA flag
;Branch if slave mode
;Push the address on stack
;check the mode flag
;Branch if in receive mode
;Push the address on stack,
;check ACK from receiver
;Stack data byte
;Transmit next byte of data
; If no ACK, branch to end
;Get value from the transmitting counter
;If no more data, branch to end
;Transmit next byte of data
;Decrease the TXCNT
2
C Data I/O Register (MBDR) in
Freescale Semiconductor