MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 273

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

15.4.12 Baud Rate Generator (MSB) Register (UBG1n)
The UBG1n register hold the eight most significant bits of the preload value the timer uses for providing
a given baud rate. The minimum value that can be loaded on the concatenation of UBG1 with UBG2 is
$0002. This register is write only and cannot be read by the CPU.
15.4.13 Baud Rate Generator (LSB) Register (UBG2n)
The UBG2n register holds the eight least significant bits of the preload value the timer uses for providing
a given baud rate. The minimum value that can be loaded on the concatenation of UBG1 with UBG2 is
$0002. This register is write only and cannot be read by the CPU.
15.4.14 Interrupt Vector Registers (UIVRn)
The UIVR registers contain the 8-bit vector number of the internal interrupt.
15.4.15 Input Port Registers (UIPn)
The UIP registers show the current state of the CTS input.
Freescale Semiconductor
IVR7–IVR0
Address MBAR + $1F0 (UIVR0)
Reset
Field
7–0
FFULL
TxRDY
Field
W
R
1
0
MBAR + $230 (UIVR1)
MBAR2 + $C30 (UIVR2)
The Interrupt Vector Bits are an 8-bit number that indicates the offset from the base of the vector table where the
address of the exception handler for the specified interrupt is located. The UIVR is reset to $0F, which indicates
an uninitialized interrupt condition.
IVR7
0
7
Table 15-17. Interrupt Mask Register (UIMRn) Field Descriptions (continued)
FIFO Full
1 Enable interrupt
0 Disable interrupt
Transmitter Ready
1 Enable interrupt
0 Disable interrupt
Table 15-18. Interrupt Vector Register (UIVRn) Field Descriptions
IVR6
0
6
Figure 15-19. Interrupt Vector Register (UIVRn)
IVR5
MCF5253 Reference Manual, Rev. 1
0
5
IVR4
0
4
Description
Description
IVR3
1
3
IVR2
Access: Supervisor or User read/write
1
2
IVR1
1
1
UART Modules
IVR0
1
0
15-27