MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 365

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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;
;
;
19.2.2
Three GPIO lines define the boot mode and device type. After initialization of the on-chip resources, the
boot loader reads the status of the GPIO lines and selects the requested device to boot from. Boot type
encoding is described in
Freescale Semiconductor
/* Disable ACRs */
moveq.l #0,d0
movec
movec
/* Initialize SRAMBAR */
move.l
movec
move.l
movec
move.l
movec
move.l
movec
/* Initialize CS0 */
move.l
move.l
move.l
move.l
move.l
move.l
move.l
move.w
jsr
bra
Boot Type Detection
I
SPI (master)
IDE (master)
I
UART (5.6448/11.2896 MHz Xtal)
UART (8.4672/16.9344/33.8688 MHz Xtal)
UART (5/10/20 MHz Xtal)
2
2
C master
C slave
d0,ACR0
d0,ACR1
#SRAM0base+1,d0;
d0,SRAMBAR
#SRAM1base+1,d0;
d0,SRAMBAR1
#___MBAR+1,d0;
d0,MBAR;
#___MBAR2+1,d0;
d0,MBAR2;
#ROMbase,d0;
d0,CSAR0;
#0xFFFF0001,d0;
d0,CSMR0;
#0x0580,d0;
d0,CSCR0;
#___SP_INIT,sp
#0x2000,SR;
_main
.;
Table
Boot Mode
19-1.
Table 19-1. Boot Detection GPIO
MCF5253 Reference Manual, Rev. 1
/* locate SRAM0, validate it! */
/* locate SRAM1, validate it! */
/* locate MBAR and validate */
/* locate MBAR2 and validate*/
/* locate ROM */
/* block size 64 KB, validate */
/* port size 16 bit, AA, 1WS */
/* enable interrupts */
/* loop in case main returns */
GPIO50
0
0
0
1
1
1
1
GPIO49
0
0
1
0
0
1
1
GPIO48
0
1
0
0
1
0
1
Boot ROM
19-3

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