MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 494

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24-32
11–10
SUSP
Field
PR
LS
9
8
7
Line Status. These bits reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use of
line status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS is
managed by the hardware.
00 SE0
01 J-state
10 K-state
11 Undefined
Reserved.
Port Reset.
In host mode, when the software writes a one to this bit the bus-reset sequence as defined in the USB Specification
Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is
different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed
in the driver.
For the USB OTG module in device mode, this bit is a read only status bit. Device reset from the USB bus is also
indicated in the USBSTS register.
1 Port is in Reset.
0 Port is not in Reset.
This field is zero if Port Power(PP) is zero.
Suspend
In host mode:
The Port Enabled bit (PE) and Suspend (SUSP) bit define the port states as follows:
0x Disable
10 Enable
11 Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking
occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend
state, the port is sensitive to resume detection.
Note: The bit status does not change until the port is suspended and that there may be a delay in suspending a port if
The module unconditionally sets this bit to zero when the software sets the Force Port Resume bit to zero. A write of
zero to this bit is ignored by the host controller. If the host software sets this bit to a one when the port is not enabled
(that is, Port enabled bit is a zero) the results are undefined.
This field is zero if Port Power(PP) is zero in host mode.
For device mode:
1 Port in suspend state.
0 Port not in suspend state. Default.
In device mode this bit is a read only status bit.
Table 24-27. Port Status and Control (PORTSC) Register Field Descriptions (continued)
there is a transaction currently in progress on the USB.
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor