MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 291

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
DOHIE
MSTR
13–10
CPOL
CPHA
BAUD
Field
BITS
7–0
15
14
9
8
QSPI_Dout
QSPI_CLK
QSPI_Din
QSPI_CS
Master mode enable.
0 Reserved, do not use.
1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.
Data output high impedance enable. Selects QSPI_Dout mode of operation.
0 Default value after reset. QSPI_Dout is actively driven between transfers.
1 QSPI_Dout is high impedance between transfers.
Transfer size—Determines the number of bits to be transferred for each entry in the queue.
Value ............. Bits per transfer
0000 ............. 16
0001–0111 .... Reserved
1000 ............. 8
1001 ............. 9
1010 ............. 10
1011 ............. 11
1100 ............. 12
1101 ............. 13
1110 ............. 14
1111 ............. 15
Clock polarity. Defines the clock polarity of QSPI_CLK.
0 The inactive state value of QSPI_CLK is logic level 0.
1 The inactive state value of QSPI_CLK is logic level 1.
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data is captured on the rising edge of QSPI_CLK and changed on the falling edge of QSPI_CLK.
1 Data is changed on the falling leading edge of QSPI_CLK and captured on the rising edge of QSPI_CLK.
Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI.
The desired QSPI_CLK baud rate is related to SYSCLK and QMR[BAUD] by the following expression:
• QMR[BAUD] = SystemClock / [2 × (desired QSPI_CLK baud rate)]
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
msb
15
15
A
Table 16-3. QSPI Mode Register (QMR) Field Descriptions
14
14
Figure 16-4. QSPI Clocking and Data Transfer Example
13
13
12
12
MCF5253 Reference Manual, Rev. 1
11
11
10
10
9
9
Description
8
8
7
7
6
6
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
5
5
Queued Serial Peripheral Interface (QSPI) Module
4
4
3
3
2
2
1
1
0
0
B
16-9