MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 200

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

IDE and Flash Media Interface
MCF5253
Figure 13-1. Bus Setup with IDE and SmartMedia Interface
In this example there is only one buffer between the MCF5253 memory bus and the IDE / SmartMedia
interface. The SDRAM (if used) is connected directly to the memory bus along with the Flash memory (if
used). The buffer therefore provides isolation (and signal buffering) between the memory bus components
and the slow, high capacitance and low impedance IDE bus. Thus allowing access to the SDRAM at the
highest memory bus speed (70MHz) possible. The buffer also prevents the SDRAM and Flash ROM
signals from going to/from the IDE / SmartMedia interfaces.
In some systems where the Flash ROM load may be excessively high or there is the requirement for
additional devices on the memory bus such as an additional SRAM or Ethernet controller. It maybe
necessary to provide further isolation and buffering of the memory bus between the MCF5253 / SDRAM.
There is provision for an additional buffer control signal in the system. The “first” bus buffer isolates the
MCF5253 / SDRAM bus from the flash ROM and any other additional devices (SRAM, Ethernet
Controller, etc.). The “second” bus buffer prevents the flash ROM signals from going to/from IDE and
SmartMedia interfaces. The IDE and SmartMedia interfaces share most signals with the ColdFire address
and data bus.
MCF5253 Reference Manual, Rev. 1
13-2
Freescale Semiconductor