MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 316

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Audio Interface Module (AIM)
17.6.1.6
The clock from the EBU signal is extracted for measurement purposes only. It cannot be used as a clock
to drive other audio interfaces like IIS. The average rate is 128 x the sampling frequency (ex. 128 * 44.1
KHz for 44.1 KHz input sampling frequency). The internal signal is used by the FreqMeas circuit (and
with suitable software) to calculate the incoming sample rate. It can also be used to calculate the offset
between the incoming SPDIF audio clock and the audio clock input at CRIN. This offset value can then
be used to calculate the necessary trim required to have the CRIN clock locked to the incoming SPDIF
clock. This is achieved via suitable external hardware and the XTRIM pin. In this way we can provide a
inherently stable and jitter free SPDIF locked clock for the rest of the application. The resultant audio clock
jitter produced is then solely a result of the stability of the crystal used as the CRIN clock source.
17.6.1.7
The IEC958 receiver is capable of extracting the User Channel bits out of the data stream. The extracted
bits are assembled in the 32-bit UChannelReceive register, with the first U-Channel bit in the MSB
position (bit 31). The interface can be configured to detect Sync patterns in the U-Channel in the case the
U-Channel contains CD subcode (CD-mode). The Sync Detection can be enabled by setting the
USyncMode bits in the CD-Subcode register
Furthermore, in CD-mode, the Q-channel receiver extracts the Q-channel CD-Subcode from the
U-Channel stream and assembles the bits in the 32-bit “QChannelReceive” with the first bit in the MSB
position.
17.6.1.8
Figure 17-10
Table 17-8
17-18
•
•
•
•
b) The EBU frequency has changed
IEC958 bit error—Set on reception of bit error. (Parity bit does not match). Reset on write to
InterruptClear register. Refer to
Internally, a symbol starting with a “1” is treated as a “data symbol”. Any consecutive 11 zeros are
treated as a “zero symbol”.
The sync detector will assume User Channel sync whenever:
(a) A sequence of 4 symbols, data-sync-sync-data, is found.
(b) 98 symbols (does not matter data or zero) after the previous “sync symbols”.
The ChannelLengthError interrupt is set when a new sync is not found at the correct distance from
the previous sync, or if UChannelReceive or QChannelReceive do not contain the correct number
of bits/bytes.
provides the description of the bit fields.
EBU Extracted Clock
Reception of User Channel and CD-Subcode Over IEC958 Receiver
U Channel Receive and Q Channel Receive Register Descriptions
illustrates the valid bits in the U Channel Receive and Q Channel Receive Registers and
MCF5253 Reference Manual, Rev. 1
Section 17.7.7, “Audio
(Table
17-11). Sync recognition is done as follows:
Interrupts”
for details.
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