MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 459

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The operation of the peripheral is described in detail in the following sections.
23.6.1
The ATA bus reset ATA_RST is asserted whenever bit 6 ata_rst_b of register ata_control is cleared to 0.
At the same time, the ATA protocol engine is reset. When this bit is set to 1, the reset is released.
23.6.2
The timing the ATA interface will operate with on the ATA bus is programmable. The 24 timing registers
at MBAR2 + 0x80 to MBAR2 + 0x817 are used for this. How these registers affect the timing parameters
on the ATA bus, is detailed in
registers at any time when the ATA bus is idle, so before reprogramming make sure that:
These 2 conditions can be accomplished by first writing dma_pending to 0, then waiting until
controller_idle is set, then reprogram the timing parameters. If dma_pending was 1 before the
reprogramming started, it should be set again after new timing is in effect to allow the drive to finish the
current DMA transfer.
It only makes sense to reprogram the bus timing in the middle of an ongoing DMA transfer when this is
necessary because the operating system wants to change the bus clock period. (Dynamic voltage frequency
scaling).
It is necessary to wait for controller_idle because a PIO read or write to the ATA bus terminates after the
bus cycle with the CPU has been terminated. If the wait for controller_idle does not occur, the new timing
values may affect a bus cycle that is still running, and cause error.
The bit iordy_en in register ata_control influences whether the ATA interface will response to the iordy
signal coming from the drive. To reprogram it, same rules as for the timing registers apply: Only allowed
when dma_pending is cleared, while controller_idle is set.
23.6.3
Access to the ATA bus in PIO mode is possible after:
To access the drive in PIO mode, simply read or write to the correct drive register. The bus cycle will be
translated to an ATA cycle, and the drive is accessed.
When drive registers are accessed while the ATA bus is in reset, the read or write is discarded, not done.
Freescale Semiconductor
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PIO mode read/write operation to the ATA bus
DMA transfers with the ATA bus
bit dma_pending in ata_control register is cleared.
bit controller_idle in interrupt_pending register is set.
ata_rst_b bit in register ata_control is set.
Timing parameters have been programmed.
Resetting ATA Bus
Programming ATA Bus Timing and iordy_en
Access to ATA Bus in PIO Mode
Section 23.4, “External Signal
MCF5253 Reference Manual, Rev. 1
Description.” It is allowed to reprogram these
Advanced Technology Attachment Controller (ATA)
23-33