MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 336

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Audio Interface Module (AIM)
The Audio Tick Interrupt was introduced to aid a busy system by allowing the Interrupt to occur after a
number of (programmable) sample pairs. In this example, the Audio Tick Interrupt has been set to trigger
after the 4th sample pair. This gives the system up to two audio sample pairs to respond and fill the FIFO.
This avoids the under-run issue. The decision to use the Audio Tick interrupt as apposed to the Empty
Interrupt is dependent on the system and the reaction time of that system. Therefore, it is not expected that
the Audio Tick Interrupt needs to be employed in all systems.
17.7.8
The processor interface registers PDOR3 and PDIR2 are equipped with a CD-ROM block
encoder/decoder. The two interfaces are fully independent. One control register is associated with the
interface.
17-38
Address MBAR2 + 0xC8
Bit Number
Reset
15–14
9, 10
W
13
11
R
Word Clock
DECODE
15
0
SWAP
CD-ROM Block Encoder and Decoder Register Descriptions
14
0
DECODE SWAP
DECODE-SYNC
DECODE
Bit Name
DECODE
DECODE
1L
ALLOW
ENABLE
ENABLE
SYNC
MODE
13
0
1R
Table 17-21. BlockControl Register Field Descriptions
12
0
Figure 17-19. Audio Transmit / Receive FIFOs
SCRAMBLE
2L
DECODE
Block decode swap control.
See note 2.
1 Sync detection enabled.
0 Sync detection disabled
See note 3.
1 Descramble enabled.
0 Escramble disabled
See note 4.
00 No CRC check
01 Mode 1
10 Mode 2, form 1
11 Mode 2, form 2
See note 1.
Figure 17-20. BlockControl Register
DE-
11
0
MCF5253 Reference Manual, Rev. 1
2R
DECODE
10
0
MODE
3L
0
9
Description
Audio Tick Interrupt
3R
Programmable
0
8
ENCODE
7
0
SWAP
4L
0
6
4R
ENCODE
ALLOW
SYNC
0
5
FIFO Empty Interrupt
5L
FIFO Under-run Interrupt
0
4
5R
SCRAMBLE
Reset
ENCODE
00
00
0
0
Freescale Semiconductor
0
3
Access: User read/write
6L
ENCODE
6R
0
2
MODE
Notes
1
2
3
4
0
1
0
0