MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 60

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Signal Description
2.24
The MCF5253 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are
multiplexed with background debug pins. See
for details.
2.25
These signals configure the MCF5253 and provide interface signals to the external system.
2.25.1
Asserting RSTI causes the MCF5253 to enter reset exception processing. When RSTI is recognized, the
data bus is tri-stated.
2.25.2
MCF5253 includes on-chip crystal oscillator. The crystal must be connected between CRIN and CROUT.
An externally generated clock signal can also be used and should be connected directly to the CRIN pin.
2.26
To exit power down mode, apply a LOW level to the WAKEUP/GPIO21 input pin.
2-14
BDM/JTAG Signals
Clock and Reset Signals
Wake-Up Signal
1
2
Reset In
System Bus Input
Rev. B enhancement.
These encodings are asserted for multiple cycles.
(Hex)
$A
$B
$C
$D
$E
$F
$7
$8
$9
PST[3:0]
Table 2-13. Processor Status Signal Encodings (continued)
(Binary)
0111
1000
1001
1010
1011
1100
1101
1110
1111
Begin execution of RTE instruction
Begin 1-byte data transfer on DDATA
Begin 2-byte data transfer on DDATA
Begin 3-byte data transfer on DDATA
Begin 4-byte data transfer on DDATA
Exception processing
Emulator mode entry exception processing
Processor is stopped, waiting for interrupt
Processor is halted
MCF5253 Reference Manual, Rev. 1
Chapter 20, “Background Debug Mode (BDM) Interface,”
2
2
Definition
2
2
Freescale Semiconductor