MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 64

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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ColdFire Core
in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes
instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and
calculates operand effective addresses, if needed.
3.2
The following sections describe the processor registers in the user and supervisor programming models.
The appropriate programming model is selected based on the privilege level (user mode or supervisor
mode) of the processor as defined by the S bit of the status register.
3.2.1
Figure 3-2
and consists of the following registers:
3.2.1.1
Registers D0–D7 are used as data registers for bit (1 bit), byte (8 bit), word (16 bit) and longword (32 bit)
operations and can also be used as index registers.
3-2
16 general-purpose 32-bit registers (D0–D7, A0–A7)
32-bit program counter (PC)
8-bit condition code register (CCR)
ColdFire Processor Memory Map and Register Definitions
shows the user Memory Map. The model is the same as the M68000 family of microprocessors
User Memory Map and Register Description
Data Registers (D0–D7)
31
MCF5253 Reference Manual, Rev. 1
Figure 3-2. User Memory Map
15
15
7
7
0
0
CCR
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
PC
Data
Registers
Address
Registers
Stack
Pointer
Program
Counter
Condition
Code
Register
Freescale Semiconductor

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