MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 148

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
uninitialized. To access the MBAR and MBAR2 peripherals, users should write MBAR and MBAR2 with
the appropriate base address and set the valid bit after system reset.
The MBAR2 base address defines a single relocatable memory block on any 1024-Mbyte boundary. If the
MBAR2 valid bit is set, the base address field is compared to the upper two bits of the full 32-bit internal
address to determine if an MBAR2 peripheral is being accessed.
Any processor bus access is first compared for SRAM match (RAMBAR registers), then it is compared
against MBAR and MBAR2. If no match is found in any of these registers, the cycle will be mapped to
the Chip Select and SDRAM units.
Table 9-1
MBAR2.
9-4
Address CPU + $C0F
31–12
Field
11–9
Reset
Reset
WP
AM
BA
C/I
8
7
5
6
W
W
R
R
BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
BA15 BA14 BA13 BA12
shows the bits in the module base address register (MBAR), and
The Base Address field defines the base address for a minimum 4 Kbyte address range.
Reserved.
The Write Protect bit is the mask bit for write cycles in the MBAR-mapped register address range.
0 Module address range is read/write
1 Module address range is read only
Reserved.
AM–Alternate Master Mask.
When AM = 0 and an alternate master actually accesses the MBAR-mapped registers; bits SC, SD, UC, and UD
(MBAR[4:1]) are “don’t cares” in the address decoding.
0 Alternate master access allowed
1 Alternate master access masked
Mask CPU Space and Interrupt Acknowledge Cycle.
0 IACK cycle mapped to MBAR space
1 IACK cycle not responded to by MBAR peripherals
31
15
–
–
30
14
–
–
Table 9-3. Module Base Address Register (MBAR) Field Descriptions
29
13
–
–
Figure 9-1. Module Base Address Register (MBAR)
28
12
–
–
27
11
–
–
MCF5253 Reference Manual, Rev. 1
26
10
–
–
25
–
–
9
WP
Description
24
–
–
8
23
–
7
–
AM
22
–
–
6
C/I
21
–
–
5
Table 9-2
SC
20
–
–
4
SD
19
–
–
3
Freescale Semiconductor
shows the bits in the
Access: User read/write
UC
18
–
–
2
UD
17
–
–
1
16
V
–
0
0