MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 237

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
EEXT
Address MBAR + $308
Field
INT
CS
AA
31
30
29
28
Reset
Reset
W
W
R
R
The Interrupt on completion of transfer field determines whether an interrupt is generated at the completion of the
transfer or occurrence of an error condition.
0 No interrupt is generated.
1 = Internal interrupt is enabled.
Enable peripheral request. Collision could occur between the START bit and the REQUEST signal when EEXT = 1.
Therefore, caution should be exercised when initiating a DMA transfer with the START bit while EEXT = 1.
0 Peripheral request is ignored.
1 Enables peripheral request to initiate transfer. Internal request is always enabled. It is initiated by writing a 1 to the
Cycle steal.
0 DMA continuous make read/write transfers until the BCR decrements to zero.
1 Forces a single read/write transfer per request. The request may be processor by setting the START bit, or
The auto-align bit and the SIZE bits determine whether the source or destination is auto-aligned. Auto alignment
means that the accesses are optimized based on the address value and the programmed size. For more information,
see
0 Auto-align disabled.
1 If the SSIZE bits indicate a larger or equivalent transfer size with respect to DSIZE, then the source accesses are
MBAR + $348
MBAR + $388
MBAR + $3C8
INT
31
15
–
–
START bit.
periphery by asserting the REQUEST signal (Can be generated by the processor).
auto-aligned. If the DSIZE bits indicate a larger transfer size than SSIZE, then the destination accesses are
auto-aligned. Source alignment takes precedence over destination alignment. If auto- alignment is enabled, the
appropriate address register increments, regardless of the state of DINC or SINC.
Section 14.7.2.2, “Auto Alignment.”
EEXT
30
14
–
–
Table 14-8. DMA Control Register (DCR) Field Descriptions
CS
29
13
–
–
Figure 14-8. DMA Control Register (DCR)—BCR24BIT = 0
AA
28
12
–
–
27
11
–
MCF5253 Reference Manual, Rev. 1
BWC
26
10
–
–
25
–
9
DAA S_RW SINC
24
–
–
8
Description
23
–
–
7
22
–
–
6
21
–
5
SSIZE
–
20
–
4
DINC
19
–
–
3
Access: User read/write
18
–
2
DSIZE
–
DMA Controller
17
–
1
START
16
–
–
0
14-9