MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 295

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

16.4.7
The command RAM is accessed using the upper byte of QDR. The QSPI cannot modify information in
command RAM.
There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables
external peripherals for transfer. The command field provides transfer operations.
Freescale Semiconductor
Address QAR[ADDR]
Address MBAR + 0x414
BITSE
CONT
DSCK
Reset
Field
Reset
DT
15
14
13
12
W
R
W
R
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when transfer is complete.
1 Chip selects remain asserted after the transfer of 16 words of data
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
CONT
a latency requirement. The delay between transfers is determined by QDLYR[DTL].
15
15
Command RAM Registers (QCR0–QCR15)
–
0
The command RAM is accessed only using the most significant byte of
QDR and indirect addressing based on QAR[ADDR].
BITSE
14
0
Table 16-7. Command RAM Registers (QCRn) Field Descriptions
14
–
Figure 16-10. Command RAM Registers (QCR0–QCR15)
13
0
DT
13
–
12
0
Figure 16-9. QSPI Data Register (QDR)
DSCK
MCF5253 Reference Manual, Rev. 1
12
–
11
0
11
–
10
0
NOTE
QSPI_CS
Description
10
–
DATA
0
9
–
9
0
8
–
8
Queued Serial Peripheral Interface (QSPI) Module
11
0
7
.
–
7
0
6
–
6
5
0
–
5
0
4
–
4
0
3
Access: User read/write
Access: User write only
–
3
2
0
–
2
0
1
–
1
16-13
0
0
0
–