MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 69

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ColdFire 5200 processors support a 1024-byte vector table aligned on any 1-megabyte address boundary
(see
the remaining 192 are user-defined interrupt vectors.
The CF2 Core processor inhibits sampling for interrupts during the first instruction of all exception
handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt
mask level contained in the status register.
Freescale Semiconductor
2. The processor determines the exception vector number. For all faults except interrupts, the
3. The processor saves the current context by creating an exception stack frame on the system stack.
4. The processor calculates the address of the first instruction of the exception handler. By definition,
Numbers(s)
Table
Vector
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from a
peripheral device. The IACK cycle is mapped to a special acknowledge address space with the
interrupt level encoded in the address.
The CF2 Core supports a single stack pointer in the A7 address register; therefore, there is no
notion of separate supervisor or user stack pointers. As a result, the exception stack frame is created
at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a
simplified fixed-length stack frame for all exceptions. The exception type determines whether the
program counter placed in the exception stack frame defines the location of the faulting instruction
(fault) or the address of the next instruction to be executed (next).
the exception vector table is aligned on a 1-megabyte boundary. This instruction address is
generated by fetching an exception vector from the table located at the address defined in the vector
base register. The index into the exception table is calculated as (4 x vector number). Once the
exception vector has been fetched, the contents of the vector determine the address of the first
instruction of the desired handler. After the instruction fetch for the first opcode of the handler has
been initiated, exception processing terminates and normal instruction processing continues in the
handler.
6–7
10
0
1
2
3
4
5
8
9
3-5). The table contains 256 exception vectors where the first 64 are defined by Freescale and
Offset (HEX)
$018-$01C
Vector
$00C
$000
$004
$008
$010
$014
$020
$024
$028
Table 3-5. Exception Vector Assignments
MCF5253 Reference Manual, Rev. 1
Stacked
Program
Counter
Fault
Fault
Fault
Fault
Fault
Fault
Next
–
–
–
1, 2
Initial stack pointer
Initial program counter
Access error
Address error
Illegal instruction
Divide by zero
Reserved
Privilege violation
Trace
Unimplemented line-a opcode
Assignment
ColdFire Core
3-7