MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 288

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are
controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is
used to drive outgoing data and to latch incoming data.
16.3.2
Baud rate is selected by writing a value from 2 to 255 into QMR[BAUD]. The QSPI uses a prescaler to
derive the QSPI_CLK rate from the system clock, SYSCLK, divided by two.
A baud rate value of zero turns off the QSPI_CLK.
The desired QSPI_CLK baud rate is related to SYSCLK and QMR[BAUD] by the following expression:
QMR[BAUD] = SYSCLK / [2 × (desired QSPI_CLK baud rate)] (SYSCLK = CORE operating
frequency / 2).
16.3.3
The QSPI supports programmable delays for the QSPI_CS signals. The time between QSPI_CS assertion
and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the
next, are both independently programmable.
The chip select to clock delay enable (DSCK) bit in command RAM, QCR[DSCK], enables the
programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD]
determines the period of delay before the leading edge of QSPI_CLK. The following expression
determines the actual delay before the QSPI_CLK leading edge:
QSPI_CS-to-QSPI_CLK delay = QCD/SYSCLK frequency
QCD has a range of 1 to 127
When QCD or DSCK equals zero, the standard delay of one-half the QSPI_CLK period is used.
The delay after transmit enable (DT) bit in command RAM enables the programmable delay period from
the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used
to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to
allow serial A/D converters to complete conversion. There are two transfer delay options: the user can
16-6
Baud Rate Selection
Transfer Delays
QMR [BAUD]
Table 16-2. QSPI_CLK Frequency as Function of SYSCLK and Baud Rate
255
16
32
2
4
8
17,500,000
8,750,000
4,375,000
2,187,500
1,093,750
546,875
70 MHz
MCF5253 Reference Manual, Rev. 1
12,000,000
6,000,000
3,000,000
1,500,000
750,000
48 MHz
94,118
SYSCLK
8,250,000
4,125,000
2,062,500
1,031,250
515,625
33 MHz
64,706
5,000,000
2,500,000
1,250,000
625,000
312,500
20 MHz
39,216
Freescale Semiconductor