MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 600

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
is not set, then the prime has failed. This can only be due to improper setup of the dQH, dTD or a setup
arriving during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit is
cleared, then the transfer descriptor can be freed and the DCD must reinterpret the setup packet.
Should a setup arrive after the data stage is primed, the device controller will automatically clear the prime
status (ENDPTSTATUS) to enforce data coherency with the setup packet.
24.11.3.5.3 Status Phase
Similar to the data phase, the DCD must create a transfer descriptor (with byte length equal zero) and prime
the endpoint for the status phase. The DCD must also perform the same checks of the ENDPTSETUPSTAT
as described above in the data phase.
24.11.3.5.4 Control Endpoint Bus Response Matrix
Table 24-86
controller state.
24-138
1
2
3
Invalid
Token
Setup
SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive.
Force Bit Stuff Error.
NYET/ACK—NYET unless the Transfer Descriptor has packets remaining according to the USB variable length protocol then
ACK.
Type
Ping
Out
In
shows the device controller response to packets on a control endpoint according to the device
STALL
STALL
STALL
Ignore
Stall
ACK
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
Error handling of data phase packets is the same as bulk packets described
previously.
Not Primed
Table 24-86. Control Endpoint Bus Response Matrix
Ignore
ACK
NAK
NAK
NAK
MCF5253 Reference Manual, Rev. 1
Receive + NYET/ACK
Endpoint State
Transmit
Primed
Ignore
ACK
ACK
NOTE
NOTE
NOTE
NOTE
3
Underflow
BS Error
Ignore
N/A
N/A
N/A
2
SYSERR
Overflow
Ignore
NAK
N/A
N/A
Freescale Semiconductor
1
Lockout
Ignore
Setup
N/A
N/A
N/A