MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 88

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Phase-Locked Loop and Clock Dividers
4.6.1
To enter Sleep mode, first put the PLL in bypass mode by clearing bit 0 of PLLCONFIG. Next, switch off
all activity by setting the SLEEPMODE bit (bit 11) in PLLCONFIG. As a result, the device will go in to a
low-power standby mode. All clocks are stopped.
4.6.2
To exit Sleep mode, apply a LOW level to the WAKEUP/GPIO21 input pin. This will power up all the
analog functions, and restart the on-chip clocks after a 10 ms time delay. Program code should then clear
bit 11 in PLLCONFIG before the low level on the WAKEUP/GPIO21 pin is removed.
If WAKEUP/GPIO21 pin is programmed as its GPO21 function, it may be impossible to exit Sleep mode
by applying low level to the WAKEUP pin.
To exit Sleep mode under this circumstance ensure the WAKEUP/GPIO21 pin is in its non-GPIO function
prior to entering Sleep mode.
4.7
During power-on reset, the value on pin A20/A24 is sensed. A 10 Kohm resistor should be connected
between these pins and VDD/GND. Depending whether a pull-up or pull-down is mounted, different
options are selected.
4.8
Many valid PLL settings exist. However, in many cases some limitations apply so that only a few typical
settings will be used. In a typical system, the following limitations may exist:
As a result, the user may select a 11.2896 MHz X-TAL as the CRIN and use the settings shown in
Table
4-8
•
•
4-9.
Users may want to run the processor at 120, 96, or 72 MHz clock frequency
MCLK1 may be 11.2896 MHz (a typical value) see
Selecting Audio_clock Input
Recommended Settings
Enter Sleep Mode
Exit Sleep Mode
X-Tal Freq
11.2896
11.2896
11.2896
MHz
A20/A24
Pin
CPU
Div
2
3
4
Pull-down: Audio clock taken from CRIN
Pull-up: Audio clock taken from LRCK3/AUDIOCLK/GPIO43 pin
Table 4-8. Audio_Clock Selection Fields
Table 4-9. Recommended PLL Settings
MCF5253 Reference Manual, Rev. 1
CRSel
0
0
0
Vcxo
Div
42
51
51
Description
Table 4-7
Div
Pll
4
4
4
in this section for further definition.
Vcxo
Out
1
1
1
Clock MHz
Freescale Semiconductor
CPU
120
96
72