MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 296

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
Queued Serial Peripheral Interface (QSPI) Module
16.4.8
The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 15MHz.
The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.
16-14
QSPI_C
To keep the chip selects asserted for all transfers, the QWR [CSIV] bit must be set to control the level that the chip selects
return to after the first transfer.
Field
11–8
7–0
S
1. Set QSPI pin functionality by the programming the PIN_CONFIG register as appropriate.
QS1: QSPICS to QSPICLK
QS2: QSPI_CLK to QSPIDOUT VALID
QS3: QSPI_CLK to QSPIDOUT HOLD
QS4: QSPI_DIN to QSPICLK SETUP
QS5: QSPI_DIN to QSPICLK HOLD
QSPICS[3:0]
QSPICLK
QSPIDOUT
QSPIDIN
1 T1 is defined as the clock period in ns.
Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be
active at once, and more than one device can be connected to each chip select.
Reserved, should be cleared.
Programming Example
Table 16-7. Command RAM Registers (QCRn) Field Descriptions (continued)
QS1
QS2
QS3
MCF5253 Reference Manual, Rev. 1
Figure 16-11. QSPI Timing
10 ns
10 ns
Min
0 ns
1T1
Description
QS4
20 ns
Max
QS5
Freescale Semiconductor