MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 75

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

If the operand alignment fails these guidelines, it is misaligned. The processor core decomposes the
misaligned operand reference into a series of aligned accesses as shown in
3.6.2
The execution times for the MOVE.{B,W} instructions are shown in
the timing for MOVE.L.
The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.
Freescale Semiconductor
Source
2. The OEP does not experience any sequence-related pipeline stalls. For ColdFire 5200 processors,
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
4. All operand data accesses are aligned on the same byte boundary as the operand size, i.e., 16 bit
(An)
Dn
An
the most common example of this type of stall involves consecutive store operations, excluding the
MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources
within the processor are marked as “busy” for two clock cycles after the final DSOC cycle of the
store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it
will be stalled until the resource again becomes available. Thus, the maximum pipeline stall
involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set
of resources and this stall does not apply.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
operands aligned on 0-modulo-2 addresses, 32 bit operands aligned on 0-modulo-4 addresses.
MOVE Instruction Execution Times
Address[1:0]
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
1(0/0)
3(1/0)
1(0/0)
X1
X1
10
Rx
Table 3-9. Move Byte and Word Execution Times
1(0/1)
1(0/1)
3(1/1)
(Ax)
Table 3-8. Misaligned Operand References
Word
Long
Long
Size
MCF5253 Reference Manual, Rev. 1
1(0/1)
1(0/1)
3(1/1)
(Ax)+
KBUS Operations
Byte, Word, Byte
NOTE
Word, Word
Byte, Byte
Destination
1(0/1)
1(0/1)
3(1/1)
-(Ax)
Table
(d
1(0/1)
1(0/1)
3(1/1)
16
,Ax)
Additional C(R/W)
3-9, while
Table
1(0/1) if write
2(0/2) if write
1(0/1) if write
2(1/0) if read
3(2/0) if read
2(1/0) if read
(d
3-8.
8
2(0/1)
2(0/1)
4(1/1)
,Ax,Xi)
Table 3-10
ColdFire Core
(xxx).wl
provides
1(0/1)
1(0/1)
3(1/1)
3-13