MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 593

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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After a Port Change Detect, the device has reached the default state and the DCD can read the PORTSCn
to determine if the device is operating in FS or HS mode. At this time, the device controller has reached
normal operating mode and DCD can begin enumeration according to the USB 2.0 Specification,
Chapter 9, Device Framework.
In some applications, it may not be possible to enable one or more pipes while in FS mode. Beyond the
data rate issue, there is no difference in DCD operation between FS and HS modes.
24.11.2.2 Suspend/Resume
24.11.2.2.1 Suspend Description
In order to conserve power, USB_DR automatically enters the suspended state when no bus traffic has
been observed for a specified period. When suspended, the USB_DR maintains any internal status,
including its address and configuration. Attached devices must be prepared to suspend at any time they are
powered, regardless of if they have been assigned a non-default address, are configured, or neither. Bus
activity may cease due to the host entering a suspend mode of its own. In addition, a USB device shall also
enter the suspended state when the hub port it is attached to is disabled.
The USB_DR exits suspend mode when there is bus activity. It may also request the host to exit suspend
mode or selective suspend by using electrical signaling to indicate remote wake-up. The ability of a device
to signal remote wake-up is optional. The USB_DR is capable of remote wake-up signaling. When the
USB_DR is reset, remote wake-up signaling must be disabled.
24.11.2.2.2 Suspend Operational Model
The USB OTG moves into the suspend state when suspend signaling is detected or activity is missing on
the upstream port for more than a specific period. After the device controller enters the suspend state, the
DCD is notified by an interrupt (assuming DC Suspend Interrupt is enabled). When the DCSuspend bit in
the PORTSCn is set to a '1', the device controller is suspended.
DCD response when the device controller is suspended is application specific and may involve switching
to low power operation.
Information on the bus power limits in suspend state can be found in USB 2.0 specification.
24.11.2.2.3 Resume
If the USB_DR is suspended, its operation is resumed when any non-idle signaling is received on its
upstream facing port. In addition, the USB_DR can signal the system to resume operation by forcing
resume signaling to the upstream port. Resume signaling is sent upstream by writing a '1' to the Resume
bit in the in the PORTSCn while the device is in suspend state. Sending resume signal to an upstream port
should cause the host to issue resume signaling and bring the suspended bus segment (one more devices)
back to the active condition.
Freescale Semiconductor
The device DCD may use the FS/HS mode information to determine the
bandwidth mode of the device.
MCF5253 Reference Manual, Rev. 1
NOTE
Universal Serial Bus Interface
24-131

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