MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 478

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24-16
ATDTW
SUTW
31–24
23–16
ASPE
Field
ASP
FS2
9–8
ITC
IAA
LR
15
14
13
12
11
10
7
6
Reserved.
Interrupt Threshold Control. The system software uses this field to set the maximum rate at which the module will
issue interrupts. ITC contains the maximum interrupt interval measured in microframes. Valid values are shown
below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
See bit 3:2 below. This is a non-EHCI bit.
Add dTD TripWire. This is a non-EHCI bit,. This bit is used as a semaphore when a dTD is added to an active (primed)
endpoint. This bit is set and cleared by the software. This bit shall also be cleared by the hardware when is state
machine is hazard region where adding a dTD to a primed endpoint may go unrecognized. More information on the
use of this bit is described in
Setup TripWire. This is a non-EHCI bit, that is present on the USB OTG module only. This bit is used as a semaphore
when the 8 bytes of setup data read extracted from a QH by the DCD. If the setup lockout mode is off (See
USBMODE) then there exists a hazard when new setup data arrives and the DCD is copying setup from the QH for
a previous setup packet. This bit is set and cleared by the software and will be cleared by the hardware when a hazard
exists. More information on the use of this bit is described in
Reserved.
Asynchronous Schedule Park Mode Enable. This bit defaults to a 0 and is R/W. The software uses this bit to enable
or disable Park mode.
1 Enabled.
0 Disabled.
Reserved.
Asynchronous Schedule Park Mode Count. This field defaults to 00 and is R/W. It contains a count of the number of
successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous
schedule before continuing traversal of the Asynchronous schedule. Valid values are 0x1 to 0x3. The software must
not write a zero to this field when Park Mode Enable is a one as this will result in undefined behavior.
Light Host/Device Controller Reset (OPTIONAL). Not Implemented. Always 0.
Interrupt on Async Advance Doorbell. This bit is used as a doorbell by the software to tell the controller to issue an
interrupt the next time it advances asynchronous schedule. The software must write a 1 to this bit to ring the doorbell.
When the controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status
bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host
controller will assert an interrupt at the next interrupt threshold.
The controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to
one. The software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield
undefined results.
This bit is used only in host mode. Writing a one to this bit when the USB OTG module is in device mode is selected
will have undefined results.
Table 24-15. USB Command Register (USBCMD) Register Field Descriptions
Section 24.12.2, “Device Operation,”
MCF5253 Reference Manual, Rev. 1
Description
Section 24.12.2, “Device Operation,”
of this manual.
Freescale Semiconductor
of this manual.