MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 646

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

FlexCAN Module
25.7.1
There are two interrupt sources for the FlexCAN module. A combined interrupt for all 32 MBs is generated
by combining all the interrupt sources from MBs. This interrupt gets generated when any of the 32 MB
interrupt sources generates a interrupt. In this case, the CPU must read the IFLAG n register to determine
which MB caused the interrupt. The other interrupt source (wired OR of bus off and error) acts in the same
way, located in the ERRSTAT n register. The bus off and error interrupt mask bits are located in the
CANCTRL n register.
25-30
2. Initialize message buffers.
3. Initialize RXGMASK n , RX14MASK n , and RX15MASK n registers for acceptance mask as
4. Initialize FlexCAN interrupt handler.
5. Clear the CANMCR n [HALT] bit. At this point, the FlexCAN will attempt to synchronize with the
a) The control/status word of all message buffers must be written as either an active or inactive
b) All other entries in each message buffer should be initialized as required.
needed.
a) Initialize the interrupt controller registers for any needed interrupts. See
b) Set the required mask bits in the IMASK n register (for all message buffer interrupts) and the
CAN bus.
message buffer.
Integration Module (SIM),”
CANCTRL n (for bus off and error interrupts).
Interrupts
MCF5253 Reference Manual, Rev. 1
for more information.
Chapter 9, “System
Freescale Semiconductor