MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 293

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

16.4.4
Freescale Semiconductor
Address MBAR + 0x40C
NEWQP
WCEFB
WCEFE
ENDQP
CPTQP
ABRTB
ABRTE
ABRTL
SPIFE
Field
CSIV
Field
11–8
Reset
7–4
3–0
7–4
12
15
14
13
12
11
10
9
8
W
R
WCEFB ABRTB
Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing the
command currently being executed is written to by the CPU with the QDR. When this bit is asserted, the write access
to QDR results in an access error.
Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to
clear QDLYR[SPE] during a transfer results in an access error.
Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by
the QSPI when a transfer completes.
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.
This field is read only.
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.
Reserved, should be cleared.
Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the interrupt, and clearing it
disables the interrupt.
Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt, and clearing it disables
the interrupt.
Reserved, should be cleared.
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and clearing it disables
the interrupt.
Reserved, should be cleared.
a transfer (that is, inactive state is 0, chip selects are active high).
a transfer (that is, inactive state is 1, chip selects are active low).
15
0
QSPI Interrupt Register (QIR)
Table 16-5. QSPI Wrap Register (QWR) Field Descriptions (continued)
14
0
Table 16-6. QSPI Interrupt Register (QIR) Field Descriptions
13
0
ABRTL WCEFE ABRTE
Figure 16-7. QSPI Interrupt Register (QIR)
12
0
MCF5253 Reference Manual, Rev. 1
11
0
10
0
Description
Description
0
9
SPIFE
8
0
Queued Serial Peripheral Interface (QSPI) Module
0
7
0
6
0
5
0
4
WCEF ABRT
0
3
Access: User read/write
0
2
0
1
SPIF
16-11
0
0