MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 207

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Under typical circumstances, CS2PRE = 0 clocks, waitCount2 = 1 or 2.
13.3
To set up the IDE interface, complete the following tasks.
Freescale Semiconductor
SmartMedia
1. Program the Chip Select 2 registers inside the chip select modules. (CSAR2, CSMR2, CSCR2).
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2. Program the IDE config1 register. Fields CS2PRE, CS2POST, BUFEN1CS2EN,
3. Program IDECONFIG2 register. Program this register as follows:
Symbol
Timing
tREA
tDH
— CSAR2, CSMR2 must be programmed to see the IDE interface in the correct part of the
— CSCR2 bit fields must be programmed as follows:
AA—0 (TA signal generated by IDECONFIG2 register logic)
WS[3:0]—not relevant
PS[1:0]—10 (16 bit port size)
BSTR, BSTW—00 (no burst read/write cycles)
BUFEN2CS2EN, and DIOR active during write are relevant. The values required for the buffer
enable signals BUFEN1CS2EN and BUFEN2CS2EN depend on the hardware configuration. If
two buffers are used in cascade, both bits must be 1. Fields CS2PRE and CS2POST are relevant
and are explained later in this section.
— TA enable 2 = ‘1’.
— IDE_IORDY enable 2 = ‘1’ if IDE_IORDY is connected from the IDE drive to the MCF5253
— IDE_IORDY enable 2 = ‘0’ if IDE_IORDY wait handshake is not used.
— WAITCOUNT2 is required and is explained later in this section.
Setting Up The IDE Interface
ColdFire address map.
chip.
If CS2POST is set to 2, every write cycle is lengthened with 1 clock. If
CS2POST is set to 3, every write cycle is lengthened with 2 clocks.
A SmartMedia interface and an IDE interface cannot be implemented
simultaneously in the same hardware application as they both share the
same read and write strobe signals on the MCF5253.
Typical Value
nS
45
20
Table 13-6. SmartMedia Timing Values (continued)
WAITCOUNT2
Controlled by
CS2POST
Setting
MCF5253 Reference Manual, Rev. 1
(waitCount2 + 3.5)T > tREA
Equation (Approximately)
NOTE
NOTE
CS2POST > tDH
To meet this timing, typical value for
cs2post is 20 ns
IDE and Flash Media Interface
Comment
–
13-9