MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 264

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15-18
TxEMP
TxRDY
Field
RB
PE
OE
FE
Address MBAR + $1C4 (USR0)
7
6
5
4
3
2
Reset
W
R
1 The transmitter-holding register is empty and ready to be loaded with a character. This bit is set when the
0 The CPU has loaded the transmitter-holding register or the transmitter is disabled.
Received Break
1 An all-zero character of the programmed length has been received without a stop bit. The RB bit is valid only when
0 No break has been received.
Framing Error
1 A stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check
0 No framing error has occurred.
Parity Error
1 When the with-parity or force-parity mode is programmed in the UMR1, the corresponding character in the FIFO
0 No parity error has occurred.
1 One or more characters in the received data stream have been lost. This bit is set on receipt of a new character
0 No overrun has occurred.
Transmitter Empty
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This
0 The transmitter buffer is not empty. Either a character is currently being shifted out or the transmitter is disabled.
Overrun Error
Transmitter Ready
MBAR + $204 (USR1)
MBAR2 + $C04 (USR2)
the RxRDY bit is set. A single FIFO position is occupied when a break is received. Additional entries into the FIFO
are inhibited until RxD returns to the high state for at least one-half bit time, which is equal to two successive
edges of the internal or external clock x 1 or 16 successive edges of the external clock x 16. The received break
circuit detects breaks that originate in the middle of a received character. However, if a break begins in the middle
of a character, it must persist until the end of the next detected character time.
occurs in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set.
was received with incorrect parity. When the multidrop mode is programmed, this bit stores the received A/D bit.
This bit is valid only when the RxRDY bit is set.
when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this
occurs, the character in the receiver-shift register and its break-detect, framing-error status, and parity error, if
any, are lost. The reset-error status command in the UCR clears this bit.
bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter-holding
register awaiting transmission.
Users can enable/disable the transmitter by programming the TCx bits in the UCR.
character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled.
Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted.
RB
0
7
Table 15-7. Status Registers (USRn) Field Descriptions
FE
0
6
Figure 15-10. Status Registers (USR0 and USR1)
MCF5253 Reference Manual, Rev. 1
PE
0
5
OE
0
4
Description
TXEMP
0
3
TXRDY
Access: Supervisor or User read/write
0
2
Freescale Semiconductor
FFULL
0
1
RXRDY
0
0