MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 493

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
WKOC
WKDS
WLCN
PHCD
19–16
15–14 Reserved
Field
PTC
PO
PP
23
22
21
20
13
12
PHY Low Power Suspend. This bit is not defined in the EHCI specification.
In host mode, the PHY can be put into Low Power Suspend – when the downstream device has been put into suspend
mode or when no downstream device is connected. Low power suspend is completely under the control of the software.
For device mode, the PHY can be put into Low Power Suspend – when the device is not running (USBCMD
Run/Stop=0b) or suspend signaling is detected on the USB. Low power suspend will be cleared automatically when the
resume signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the CLK signals, then PHCD must be set.
Wake on Over-current Enable. Writing this bit to a one enables the port to be sensitive to over-current conditions as
wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is (OTG/host mode only) for use by an external power control circuit.
Wake on Disconnect Enable. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up
events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
Wake on Connect Enable. Writing this bit to a one enables the port to be sensitive to device connects as wake-up
events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
Port Test Control. Any other value than zero indicates that the port is operating in test mode.
0000 Normal operation
0001 J_STATE
0010 K_STATE
0011 SEQ_NAK
0100 Test packet
0101 FORCE_ENABLE
0110–1111 Reserved.
Refer to Chapter 7 of the USB Specification Revision 2.0 [3] for details on each test mode.
Port Owner. This bit unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. The system software uses this field to
release ownership of the port to a selected the module (in the event that the attached device is not a high-speed device).
The software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that
an internal companion controller owns and controls the port.
Port owner hand-off is not implemented in this design, therefore this bit is always 0.
Port Power. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port(that
is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port, the PP bit in each affected port is transitioned by the
host controller driver from a one to a zero (removing power from the port).
This feature is implemented in the host/OTG controller (PPC = 1).
For the USB OTG module in a device-only implementation port power control is not necessary, thus PPC and PP = 0.
Table 24-27. Port Status and Control (PORTSC) Register Field Descriptions (continued)
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-31