MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 191

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

11.6.3
TCN is a memory-mapped 16-bit up counter that users can read at any time. A read cycle to TCN yields
the current timer value and does not affect the counting operation.
A write of any value to TCN causes it to reset to all zeros.
11.6.4
The TER is an 8-bit register that reports events the timer recognizes. When the timer recognizes an event,
it sets the appropriate bit in the TER, regardless of the corresponding interrupt-enable bits (ORI and CE)
in the TMR.
TER appears as a memory-mapped register and can be read at any time.
Writing a one to a bit will clear it (writing a zero does not affect the bit value); more than one bit can be
cleared at a time. The REF and CAP bits must be cleared before the timer will negate the IRQ to the
interrupt controller. Reset clears this register.
Freescale Semiconductor
Address MBAR+$14C
Field
REF
CAP
7–2
Address MBAR+$151
1
0
Reset
Reset
W
R
W
R
Reserved for future use. These bits are currently 0 when read.
If a one is read from the Output Reference Event bit, the counter has reached the TRR value. The ORI bit in the
TMR enables the interrupt request caused by this event. Writing a one to this bit will clear the event condition.
Not applicable
MBAR+$18C
MBAR+$191
Timer Counters (TCN0, TCN1)
15
Timer Event Registers (TER0, TER1)
0
0
7
14
0
13
0
Table 11-3. Timer Event Register (TERn) Field Descriptions
6
0
12
0
Figure 11-5. Timer Event Register (TERn)
16-BIT TIMER COUNTER VALUE (COUNT15–COUNT0)
11
0
Figure 11-4. Timer Counter (TCNn)
MCF5253 Reference Manual, Rev. 1
10
0
0
5
0
9
8
0
0
4
Description
0
7
0
6
0
3
0
5
Access: Supervisor or User read/write
Access: Supervisor or User read/write
4
0
0
2
General Purpose Timer Modules
0
3
REF
2
0
1
0
0
1
CAP
0
0
0
0
11-5