MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 355

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Address MBAR+ $28C (MBSR)
Field
IAAS
SRW
ICF
IBB
IAL
Reset
7
6
5
4
3
2
W
R
While one byte of data is being transferred, the Data Transferring Bit bit is cleared. It is set by the falling edge of the 9th
clock of a byte transfer.
1 Transfer complete
0 Transfer in progress
When its own specific address (I
Bit is set. The CPU is interrupted provided the IIEN is set. Next, the CPU must check the SRW bit and set its TX/RX
mode accordingly. Writing to the I
1 Addressed as a slave
0 Not addressed
The Bus Busy Bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is
detected, it is cleared.
1 Bus is busy
0 Bus is idle
Hardware sets the Arbitration Lost bit (IAL) when the arbitration procedure is lost. Arbitration is lost in the following
circumstances:
This bit must be cleared by software by writing a zero to it.
Reserved
When IAAS is set, the Slave Read/Write bit indicates the value of the R/W command bit of the calling address sent from
the master. This bit is valid only when:
Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.
1 Slave transmit, master reading from slave
0 Slave receive, master writing to slave
• SDA sampled as low when the master drives a high during an address or data-transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
• A complete transfer has occurred and no other transfers have been initiated.
• I
MBAR2+ $44C (MBSR2)
2
C is a slave and has an address match.
ICF
1
7
IAAS
0
6
Table 18-6. MBSR Register Field Descriptions
2
C Address Register) is matched with the calling address, the Addressed as a Slave
2
C Control Register clears this bit.
MCF5253 Reference Manual, Rev. 1
IBB
0
5
Figure 18-7. MBSR Register
IAL
0
4
Description
3
0
SRW
Access: Supervisor or User read/write
0
2
IIF
0
1
I
2
C Modules
RXAK
1
0
18-11