MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 645

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.7
Initialization of the FlexCAN includes the initial configuration of the message buffers and configuration
of the CAN communication parameters following a reset, as well as any reconfiguration that may be
required during operation. The FlexCAN module may be reset in three ways:
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The CANMCR n [SOFT_RST] bit
remains asserted while soft reset is pending, so software can poll this bit to know when the reset has
completed. Also, soft reset can not be applied while clocks are shut down in any of the low power modes.
The low power mode should be exited and the clocks resumed before applying soft reset.
The clock source, CANCTRL n [CLK_SRC], should be selected while the module is in disable mode. After
the clock source is selected and the module is enabled (CANMCR n [MDIS] bit cleared), the FlexCAN
automatically enters freeze mode. In freeze mode, the FlexCAN is un-synchronized to the CAN bus, the
CANMCR n register’s HALT and FRZ bits are set, the internal state machines are disabled, and the
CANMCR n register’s FRZ_ACK and NOT_RDY bits are set. The CAN n TX pin is in recessive state and
the FlexCAN does not initiate any transmission or reception of CAN frames. Note that the message buffers
are not affected by reset, so they are not automatically initialized.
For any configuration change/initialization, the FlexCAN must be in freeze mode (see
“Freeze
Freescale Semiconductor
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•
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1. Initialize all operation modes in the CANCTRL n register.
Device level hard reset—resets all memory mapped registers asynchronously
Device level soft reset—resets some of the memory mapped registers synchronously (refer to
Table 25-1
CANMCR n [SOFT_RST] bit—has the same effect as the device level soft reset
a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW.
b) Select the S-clock rate by programming the PRESDIV field.
c) Select the internal arbitration mode via the LBUF bit.
Mode”). The following is a generic initialization sequence applicable to the FlexCAN module:
FlexCAN Initialization Sequence
to see which registers are affected by soft reset)
Table 25-15. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
MCF5253 Reference Manual, Rev. 1
Time Segment 2
2
3
4
5
6
7
8
Re-synchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
Section 25.3.2.2,
FlexCAN Module
25-29