MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 394

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
20.3.4.1.11 Read Debug Module Register (RDMREG)
RDMREG reads the selected debug module register and return the 32-bit result. The only valid register
selection for the RDMREG command is the CSR (DRc = $0).
DRc encoding:
Command Sequence:
Operand Data:
None
Result Data:
The contents of the selected debug register are returned as a longword value. The data is returned most
significant word first.
20.3.4.1.12 Write Debug Module Register (WDMREG)
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. The DSCLK signal must be inactive while debug module register writes from the
CPU accesses are performed using the WDEBUG instruction.
20-24
DRc[3:0]
$1-$F
$0
Figure 20-24. Read Debug Module Register Command Sequence
Configuration/Status
Reserved
Figure 20-23. RDMREG Command/Result Register
Figure 20-25. WDMREG BDM Command Register
Table 20-15. Definition of DRc Encoding—Read
RDMREG
Debug Register Definition
???
MCF5253 Reference Manual, Rev. 1
MS Result
“Illegal”
XXX
XXX
Mnemonic
CSR
–
“Not Ready”
Next CMD
Next CMD
LS Result
Initial State
Freescale Semiconductor
$0
–