MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 185

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Address MBAR + 0x96 (CSCR1)
BSTW
15–14
13–10
BSTR
Field
Reset
7–6
2–0
WS
AA
PS
9
8
5
4
3
W
R
MBAR + 0xA2 (CSCR2)
MBAR + 0xAE (CSCR3)
MBAR + 0xBA (CSCR4)
Reserved.
The Wait States field defines the number of wait states that are inserted before an internal transfer acknowledge is
generated. If the AA bit is cleared, TA must be asserted by the external system regardless of the number of wait
states generated.
Reserved.
The Auto-Acknowledge Enable field determines the assertion of the internal transfer-acknowledge for accesses
specified by the chip select address.
0 No internal transfer acknowledge (TA) is asserted.
1 Internal acknowledge (TA) is asserted as specified by WS[3:0].
The Port Size field specifies the width of the data associated with each chip select. It determines where data is driven
during write cycles and where data is sampled during read cycles. Port size should always be programmed to
16-bits.
00 Reserved.
01 Reserved.
10 16-bit port size–Data sampled and driven on D[31:16] only.
11 16-bit port size–Data sampled and driven on D[31:16] only.
Note: A0 is not available on the external bus.
Reserved.
The Burst Read Enable field specifies whether burst reads are used for the memory associated with each chip
select.
0 Breaks data larger than the specified port size into individual non-burst reads that equals the specified port size.
1 Enables burst read of data larger than the specified port size.
The Burst Write Enable field specifies whether burst writes are used for the memory associated with each chip
select.
0 Break data larger than the specified port size into individual non-burst writes that equals the specified port size.
1 Enables burst write of data larger than the specified port size.
Reserved.
15
–
For example, a longword read from an 16-bit port would be broken into two individual wordreads.
For example, a longword write to an 16-bit port would be broken into two individual word writes.
14
–
Table 10-5. Chip Select Control Register (CSCRx) Field Descriptions
WS3 WS2 WS1 WS0
13
–
Figure 10-4. Chip Select Control Registers (CSCRx)
12
–
11
–
MCF5253 Reference Manual, Rev. 1
10
–
–
9
AA
–
8
Description
PS1
–
7
PS0
–
6
–
5
BSTR
–
4
BSTW
–
3
Access: User read/write
Chip Select Module
–
2
–
1
10-9
0
0