MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 248

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.1.1
The communication channel provides a full duplex asynchronous receiver and transmitter using an
operating frequency derived from the system clock.
The transmitter accepts parallel data from the CPU; converts it to a serial bit stream; inserts the appropriate
start, stop, and optional parity bits; then outputs a composite serial data stream on the channel transmitter
serial data output (TxD). Refer to
The receiver accepts serial data on the channel receiver serial data input (RxD); converts it to parallel
format; checks for a start bit, stop bit, parity (if any), or any error condition; and transfers the assembled
character onto the bus during read operations. The receiver can be polled or interrupt driven. Refer to
Section 15.3.2.2, “Receiver,”
15.1.2
The 16-bit timer, clocked by the system clock, can function as an asynchronous x16 clock. The baud-rate
timer is part of each UART and not related to the ColdFire timer modules.
15.1.3
An internal interrupt request signal (IRQ) notifies the MCF5253 interrupt controller of an interrupt
condition. The output is the logical NOR of all (as many as four) unmasked interrupt status bits in the
UART Interrupt Status Register (UISR). The UART Interrupt Mask Register (UIMR) can be programmed
to determine which interrupts will be valid in the UISR.
15-2
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Independently programmable receiver and transmitter clock source
Programmable data format
— Five to eight data bits plus parity
— Odd, even, no parity, or force parity
— .563 to 2 stop bits in x16 mode (asynchronous)/1or 2 stop bits in synchronous mode
Programmable channel modes:
— Normal (full duplex)
— Automatic echo
— Local loopback
— Remote loopback
Automatic wakeup mode for multidrop applications
Four maskable interrupt conditions
Parity, framing, break, and overrun error detection
False start bit detection
Line-break detection and generation
Detection of breaks originating in the middle of a character
Start/end break interrupt/status
Serial Communication Channel
Baud-Rate Generator/Timer
Interrupt Control Logic
for additional information.
Section 15.3.2.1, “Transmitter,”
MCF5253 Reference Manual, Rev. 1
for additional information.
Freescale Semiconductor