MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 257

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

15.3.3.2
In this mode, TxD is internally connected to RxD. This mode is useful for testing the operation of a local
UART module channel by sending data to the transmitter and checking data assembled by the receiver. In
this manner, correct channel operations can be assured. Both transmitter and CPU-to-receiver
communications continue normally in this mode. While in this mode, the RxD input data is ignored, the
TxD is held marking, and the receiver is clocked by the transmitter clock. The transmitter must be enabled
but not the receiver.
15.3.3.3
In this mode, the channel automatically transmits received data on the TxD output on a bit-by-bit basis.
The local CPU-to-transmitter link is disabled. This mode is useful for testing remote channel receiver and
transmitter operation. While in this mode, the receiver clocks the transmitter.
Freescale Semiconductor
Local Loopback Mode
Remote Loopback Mode
Because the receiver is not active, the CPU cannot read received data. All
status conditions are inactive. Received parity is not checked and is not
recalculated for transmission. Stop bits are transmitted as received. A
received break is echoed as received until the next valid start bit is detected.
CPU
CPU
CPU
Figure 15-7. Looping Modes Functional Diagram
(c) Remote Loopback
MCF5253 Reference Manual, Rev. 1
(a) Automatic Echo
(b) Local Loopback
Rx
Tx
Rx
Tx
Tx
Rx
NOTE
Disabled
Disabled
Disabled
Disabled
Disabled
RxD Input
TxD
Output
RxD Input
TxD
Output
RxD Input
TxD
Output
UART Modules
15-11