MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 623

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
NOTRDY
Offset MBAR2 0x1000 (CANMCR0)
Reset
Reset
MDIS
HALT
Field
FRZ
31
30
29
28
27
26
W
W
R
R
MBAR2 0x2000 (CANMCR1)
MDIS FRZ
31
15
1
0
0
Module disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the
FlexCAN clocks that drive the CAN interface and Message Buffer sub-module. This is the only bit in CANMCRn not
affected by soft reset. See
0 Enable the FlexCAN module, clocks enabled
1 Disable the FlexCAN module, clocks disabled
Freeze mode enable. When set, the FlexCAN can enter freeze mode when the BKPT line is asserted or the HALT
bit is set. Clearing this bit causes the FlexCAN to exit freeze mode. Refer to
more information.
0 FlexCAN ignores the BKPT signal and the CANMCRn[HALT] bit.
1 FlexCAN module enabled to enter debug mode.
Reserved, should be cleared.
Halt FlexCAN. Setting this bit puts the FlexCAN module into freeze mode. It has the same effect as assertion of the
BKPT signal. This bit is set after reset and should be cleared after initializing the message buffers and control
registers. FlexCAN message buffer receive and transmit functions are inactive until this bit is cleared. While in
freeze mode, the CPU has write access to the error counter register (ERRCNTn), that is otherwise read-only.
0 The FlexCAN operates normally
1 FlexCAN enters freeze mode if FRZ = 1
FlexCAN not ready. This bit indicates that the FlexCAN is either in disable or freeze mode. This bit is read-only and
it is cleared once the FlexCAN exits these modes.
0 FlexCAN is either in normal mode, listen-only mode, or loop-back mode.
h1FlexCAN is in disable or freeze mode.
Reserved, should be cleared.
30
14
Table 25-2. FlexCAN Configuration Register (CANMCRn) Field Descriptions
1
0
0
29
13
0
0
0
0
Figure 25-4. FlexCAN Configuration Register (CANMCRn)
HALT
28
12
1
0
0
NOT
RDY
Section 25.3.2.3, “Module Disabled Mode,”
27
11
1
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
0
0
SOFT
RST
25
0
0
0
9
ACK SUPV
FRZ
24
0
0
0
8
Description
23
1
0
0
7
22
0
0
0
0
6
for more information.
21
0
0
0
0
5
Section 25.3.2.2, “Freeze Mode,”
LPM
ACK
20
1
1
4
Access: Supervisor read/write
19
0
0
3
1
MAXMB
18
0
0
1
2
FlexCAN Module
17
0
0
1
1
for
25-7
16
0
0
0
1