MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 508

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
The DMA controllers must access both control information and packet data from DMA cache memory.
The control information is contained in link list based queue structures. The DMA controllers have state
machines that are able to parse data structures defined in the EHCI specification. In host mode, the data
structures are EHCI compliant and represent queues of transfers to be performed by the host controller,
including the split-transaction requests that allow an EHCI controller to direct packets to FS and LS speed
devices. In device mode, the data structures designed to be similar to those in the EHCI specification and
are used to allow device responses to be queued for each of the active pipes in the device.
The DMA controller can access only the DMA_CACHE memory. Therefore, all data and data structures
that are read/written by the DMA engine must be reside in this memory. The USB module has priority on
this memory and will get access 1 clock cycle after the request.
24.7.2
The FIFO RAM controller is used for context information and to control FIFOs between the protocol
engine and the DMA controller. These FIFOs decouple the system processor/memory bus requests from
the extremely tight timing required by USB.
The use of the FIFO buffers differs between host and device mode operation. In host mode, a single data
channel is maintained in each direction through the buffer memory. In device mode, multiple FIFO
channels are maintained for each of the active endpoints in the system.
In host mode, the module uses a 256-byte TX buffer and a 128-byte RX buffer. Device operation uses a
single 128-byte RX buffer and a 64-byte TX buffer for each endpoint.
24.7.3
The module interfaces to the internal PHY. The primary function of the port controller block is to isolate
the rest of the module from the transceiver, and to move all of the transceiver signaling into the primary
clock domain of the module. This allows the module to run synchronously with the system processor and
it's associated resources.
24.8
This section defines the interface data structures used to communicate control, status, and data between
HCD (software) and the Enhanced Host Controller (hardware). The data structure definitions in this
section support a 32-bit memory buffer address space. The interface consists of a Periodic Schedule,
Periodic Frame List, Asynchronous Schedule, Isochronous Transaction Descriptors, Split-transaction
Isochronous Transfer Descriptors, Queue Heads, and Queue Element Transfer Descriptors.
The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the
host controller interface. The asynchronous list is the root for all the bulk and control transfer type support.
Isochronous data streams are managed using Isochronous Transaction Descriptors. Isochronous
split-transaction data streams are managed with Split-transaction Isochronous Transfer Descriptors. All
Interrupt, Control, and Bulk data streams are managed via queue heads and Queue Element Transfer
Descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and
to reduce (on average) the number of memory accesses needed to execute a USB transaction.
24-46
Host Data Structures
FIFO RAM Controller
PHY Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor