MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 241

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

14.5
The DMA channel supports processor and periphery requests. Bus utilization can be minimized for either
processor or periphery request by selecting between cycle-steal and continuous modes. The DCR[EEXT]
field determines the request-generation method for each channel.
14.5.1
The DMA is in cycle-steal mode if the CS field (DCR[29]) is set. In this mode, only one complete transfer
from source to destination takes place for each request. Depending on the state of the EEXT field
(DCR[30]), the request can be either processor or periphery. Processor request is selected by setting the
START bit (DCR[16}). Periphery request is initiated by asserting the REQUEST signal while the EEXT
bit is set.
14.5.2
The DMA is in continuous mode If the CS field (DCR[29]) is cleared. After an internal or external request
is asserted, the DMA continuously transfers data until the byte count register (BCR) reaches zero or the
DONE bit (DSR[0]) is set.
The continuous mode can operate at maximum or limited rate. The maximum rate of transfer can be
achieved if the bandwidth control BWC field (DCR[27:25]) is programmed to 000. Then the active DMA
channel continues until the BCR decrements to zero or the DONE bit is set.
A limited rate can be achieved by programming the BWC field to any value other than 000. The DMA
performs the specified number of transfers, then relinquishes control of the bus. The DMA negates its
internal bus request on the last transfer before the BCR reaches a multiple of the boundary specified in the
BWC field. On transfer completion, the DMA asserts its bus request again to regain bus ownership at the
earliest opportunity, as determined by the internal bus arbiter. The minimum time that the DMA loses bus
control is one bus cycle.
14.6
Each DMA channel supports dual-address transfers. The dual-address transfer mode consists of a source
operand read and a destination operand write.
14.6.1
The DMA controller module begins a dual-address transfer sequence when the DAA bit (DCR[24]) is
cleared during a DMA request. If no error condition exists, the REQ bit (DSR[2]) is set.
14.6.1.1
The DMA controller module will drive the value in the source address register (SAR) onto the internal
address bus. If the SINC bit (DCR[22]) is set, then the SAR increments by the appropriate number of bytes
upon a successful read cycle. When the appropriate number of read cycles completes successfully, the
DMA initiates the write portion of the transfer.
Freescale Semiconductor
Transfer Request Generation
Data Transfer Modes
Cycle-Steal Mode
Continuous Mode
Dual-Address Transaction
Dual-Address Read
MCF5253 Reference Manual, Rev. 1
DMA Controller
14-13