MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 595

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.11.3.1.1 Stalling
There are two occasions where the USB_DR may need to return to the host a STALL.
The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0
Specification, Chapter 9, Device Framework. A functional stall is only used on non-control endpoints and
can be enabled in the device controller by setting the endpoint stall bit in the ENDPTCTRLn register
associated with the given endpoint and the given direction. In a functional stall condition, the device
controller will continue to return STALL responses to all transactions occurring on the respective endpoint
and direction until the endpoint stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device
controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD
should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLn register can
ensure that both stall bits are set at the same instant.
24.11.3.2 Data Toggle
Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe.
For more information on data toggle, refer to the USB 2.0 specification.
24.11.3.2.1 Data Toggle Reset
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a '1' to the data toggle reset bit in the ENDPTCTRLn register. This should only be
necessary when configuring/initializing an endpoint or returning from a STALL condition.
Freescale Semiconductor
SETUP packet received by a non-control endpoint.
IN/OUT/PING packet received by a non-control endpoint.
IN/OUT/PING packet received by a non-control endpoint.
SETUP packet received by a control endpoint.
IN/OUT/PING packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint.
Endpoint Type
Endpoint Stall
Any write to the ENDPTCTRLn register during operational mode must
preserve the endpoint type field (that is, perform a read-modify-write).
Table 24-81. Device Controller Endpoint Initialization (continued)
Table 24-82. Device Controller Stall Response Matrix
USB Packet
Field
MCF5253 Reference Manual, Rev. 1
NOTE
00 Control
01 Isochronous
10 Bulk
11 Interrupt
0
Endpoint
Stall Bit
N/A
N/A
1
0
1
0
STALL Bit
Effect on
Cleared
None
None
None
None
None
Value
Universal Serial Bus Interface
ACK/NAK/NYET
ACK/NAK/NYET
USB Response
STALL
STALL
STALL
ACK
24-133