MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 177

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10
Chip Select Module
The Chip Select Module provides user-programmable control of the three chip select outputs, two buffer
enable outputs and one output-enable signal. This chapter describes the operation, memory map, and
register descriptions of the Chip Select module, including the chip select address, mask, and control
registers.
10.1
10.2
The MCF5253 provides three programmable chip selects that can directly interface with SRAM, EPROM,
EEPROM, and peripherals. Chip select CS2 provides separate read and write strobes for an AT-bus
peripheral interface, and uses IORDY signalling to insert wait states.
10.2.1
CS0 is the first chip select and it addresses either the on-chip or external boot memory. At power-on reset,
all bus cycles are mapped to the CS0. This allows the boot memory to be defined at any address space.
CS0 is the only chip select initialized at reset.
During power-on reset, pin A23 is sensed. A resistor should be connected between this pin and VDD or
GND. Depending whether a pull-up or pull-down is mounted, different options are selected as described
in
Freescale Semiconductor
Table
•
•
•
•
•
•
Three programmable chip select outputs (CS0/CS4, CS1 and CS2 (IDE_DIOR and IDE_DIOW))
IORDY and TA handshake pins
Two programmable buffers enable signals for glueless interface to bus buffers
Address masking for memory block sizes from 64 Kbytes to 4Gbytes
Programmable wait states
Port size is 16 bits
10-1.
Chip Select Features
Chip Select Signals
CS0/CS4
A23
Pin
Pull-up: Boot from memory connected to CS0/CS4. CS0/CS4 function is CS0
Pull-down: Boot from on-chip boot ROM. CS0/CS4 function becomes CS4
MCF5253 Reference Manual, Rev. 1
Table 10-1. CS0 Operation
Description
10-1