MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 266

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.4.5
The UCR supplies commands to the UART. Multiple commands can be specified in a single write to the
UCR if the commands are not conflicting. For example, reset-transmitter and enable-transmitter
commands cannot be specified in a single command.
15.4.5.1
Bits MISC3 through MISC0 select a single command as listed in
15.4.5.1.1
The reset mode register pointer command causes the mode register pointer to point to UMR1.
15.4.5.1.2
The reset receiver command resets the receiver. The receiver is immediately disabled, the FFULL and
RxRDY bits in the USR are cleared, and the receiver FIFO pointer is reinitialized. All other registers are
unaltered. Use this command instead of the receiver-disable command whenever the receiver
configuration is changed (it places the receiver in a known state).
15-20
Address MBAR + $1C8 (UCR0)
Reset
W
R
MBAR + $208 (UCR1)
MBAR2 + $C08 (UCR2)
Command Registers (UCRn)
Miscellaneous Commands
Reset Mode Register Pointer
Reset Receiver
0
7
MISC2
MISC2
0
0
0
0
1
1
1
1
0
6
Figure 15-12. Command Register (UCRn)
MISC1
MCF5253 Reference Manual, Rev. 1
Table 15-9. MISCx Control Bits
0
0
1
1
0
0
1
1
MISC1
0
5
MISC0
0
1
0
1
0
1
0
1
MISC0
0
4
No Command
Reset Mode Register Pointer
Reset Receiver
Reset Transmitter
Reset Error Status
Reset Break-Change Interrupt
Start Break
Stop Break
Command
TC1
0
3
Table
15-9.
TC0
0
2
Freescale Semiconductor
Access: User write only
RC1
0
1
RC0
0
0