MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 643

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

25.6.7
The value of TIMER n is sampled at the beginning of the identifier field on the CAN bus. For a message
being received, the time stamp will be stored in the TIMESTAMP entry of the receive message buffer at
the time the message is written into that buffer. For a message being transmitted, the TIMESTAMP entry
will be written into the transmit message buffer once the transmission has completed successfully.
The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This
feature allows network time synchronization to be performed. See the CANCTRL n [TSYN] bit.
25.6.8
The FlexCAN module CANCTRL n register configures the bit timing parameters required by the CAN
protocol. The CLK_SRC, PRESDIV, RJW, PSEG1, PSEG2, and the PROPSEG fields allow the user to
configure the bit timing parameters.
The CANCTRL n [CLK_SRC] bit defines whether the module uses the internal bus clock or the output of
the crystal oscillator via the CRIN pin. The crystal oscillator clock should be selected whenever a tight
tolerance (up to 0.1%) is required for the CAN bus timing. The crystal oscillator clock has better jitter
performance than PLL generated clocks. The value of this bit should not be changed, unless the module is
in disable mode (CANMCR n [MDIS] bit is set)
Careful consideration should be given when selecting the external clocking scheme, the audio sections
may require specific input frequencies—for example, 11.2896MHz, that are not suited to meeting the CAN
timing requirements, particularly at high speed communication, therefore it may required to use the
external audio clock pin when using the CAN modules.
The PRESDIV field controls a prescaler that generates the serial clock (S-clock), whose period defines the
time quantum used to compose the CAN waveform. A time quantum is the atomic unit of time handled by
the CAN engine.
A bit time is subdivided into three segments
1. For further explanation of the underlying concepts please refer to ISO/DIS 11519–1, Section 10.3. Reference also the Bosch
Freescale Semiconductor
CAN 2.0A/B protocol specification dated September 1991 for bit timing.
•
•
Eighth (last) bit of the error frame delimiter or overload frame delimiter
SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen within
this section.
Time Stamp
Bit Timing
Oscillator Clock (CRIN)
Internal Bus Clock
(SYSCLK)
Figure 25-14. CAN Engine Clocking Scheme
CANCTRLn[CLK_SRC]
f
MCF5253 Reference Manual, Rev. 1
Tq
1
0
=
SYCLK or EXTAL
---------------------------------------------- -
(
1
PRESDIV + 1
(reference
Figure 25-15
)
Prescaler
(1 .. 256)
and
Table
25-14):
S clock
FlexCAN Module
Eqn. 25-5
25-27