MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 422

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

USB, ATA DMA, and Clock Integration Module
22-2
DMAEND
CPUEND
RTCCLR
RTCPL
31–15
ADTD
ADTA
Field
URIP
URIC
URIE
ADIP
ADIC
ADIE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved, must be cleared.
Reserved, this bit must always be set to 1.
USB resume interrupt pending
0 USB resume interrupt not pending
1 USB resume interrupt pending
USB resume interrupt clear. Always reads 0
0 no effect
1 clear USB resume interrupt
USB resume interrupt enable
0 Pending USB resume interrupt not sent to CPU
1 Pending USB resume interrupt forward to CPU
Reserved, should always be set to 0.
Reserved, should always be set to 0.
Real-time clock power loss. To clear this bit, set the RTCCLR bit and then clear the RTCCLR bit.
0 RTC maintaining time OK
1 Power lost to RTC
Real-time clock power loss clear.
0 No action
1 Clears the RTCPL bit
Endianess of DMA access to ATA
0 Little endian
1 Big endian
Endianess of CPU access to ATA
0 Little endian
1 Big endian
ATA DMA interrupt pending.
0 ATA DMA interrupt not pending
1 ATA DMA interrupt pending
ATA DMA interrupt clear. This bit always reads 0, and clearing this bit has no affect.
Write:
0 No affect
1 Clears ATA DMA interrupt
ATA DMA interrupt enable.
0 ATA DMA interrupt disabled
1 ATA DMA interrupt will interrupt CPU
ATA DMA channel transfer direction.
0 RAM to ATA
1 ATA to RAM
ATA DMA transfer active.
1 ATA DMA armed. Will transfer data when needed as long as atadma_count > 0.
0 ATA DMA blocked. WIll not transfer data.
Table 22-2. Miscellaneous Configuration Register (MISCCR) Field Descriptions
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor