MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 533

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

each micro-frame, if the periodic schedule is enabled (see) then the host controller must execute from the
periodic schedule before executing from the asynchronous schedule. It will only execute from the
asynchronous schedule after it encounters the end of the periodic schedule. The host controller traverses
the periodic schedule by constructing an array offset reference from the PERIODICLISTBASE and the
FRINDEX registers (see
schedule data structures.
The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its
T-bit set. When the host controller encounters a T-Bit set during a horizontal traversal of the periodic list,
it interprets this as an End-Of-Periodic-List mark. This causes the host controller to cease working on the
periodic schedule and transitions immediately to traversing the asynchronous schedule. Once this
transition is made, the host controller executes from the asynchronous schedule until the end of the
micro-frame.
When the host controller determines that it is time to execute from the asynchronous list, it uses the
operational register ASYNCLISTADDR to access the asynchronous schedule, as shown in
The ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the
host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue
head referenced by the ASYNCLISTADDR register. The software must set queue head horizontal pointer
T-bits to a zero for queue heads in the asynchronous schedule.
See
Freescale Semiconductor
Section 24.9.9, “Asynchronous
31
Periodic Frame List Base
31
AsyncListAddr
Operational
Registers
USBCMD
USBSTS
Address
Figure 24-44. General Format of Asynchronous Schedule List
•
•
•
•
•
•
Figure 24-43. Derivation of Pointer into Frame List Array
Figure
24-43). It fetches the element and begins traversing the graph of linked
Periodic Frame List Element
Schedule” for complete operational details.
MCF5253 Reference Manual, Rev. 1
DWord-Aligned
Address
12
13 12
12 11
H
Frame Index Register
3 2
2 1 0
0
Universal Serial Bus Interface
Periodic Frame
List
•
•
•
Figure
24-44.
24-71