MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 416

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

IEEE 1149.1 Test Access Port (JTAG)
21.5
21.5.1
The MCF5253 IEEE 1149.1A Standard implementation uses a 4-bit instruction-shift register without
parity. This register transfers its value to a parallel hold register and applies one of eight possible
instructions on the falling edge of TCK when the TAP state machine is in the update-IR state. To load the
instructions into the shift portion of the register, place the serial data on the TDI pin prior to each rising
edge of TCK.
Table 21-2
The IEEE 1149.1A Standard requires the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions.
IDCODE, CLAMP, HIGHZ are optional standard instructions that the MCF5253 implementation supports
and are described in the IEEE Standard 1149.1A. The RINGOSC and ORGATE are user defined
instructions only used for device test during manufacturing.
21.5.1.1
The external test instruction (EXTEST) selects the boundary-scan register. The EXTEST instruction
forces all output pins and bidirectional pins configured as outputs to the preloaded fixed values (with the
SAMPLE/PRELOAD instruction) and held in the boundary-scan update registers. The EXTEST
instruction can also configure the direction of bidirectional pins and establish high-impedance states on
some pins. The EXTEST instruction becomes active on the falling edge of TCK in the update-IR state
when the data held in the instruction-shift register is equivalent to hex 0.
21.5.1.2
The IDCODE instruction selects the 32-bit IDcode register for connection as a shift path between the TDI
pin and the TDO pin. This instruction lets users interrogate the MCF5253 to determine its version number
21-6
Instruction ABBR
PRELOAD
RINGOSC RING Optional
SAMPLE/
ORGATE
EXTEST
IDCODE
BYPASS
CLAMP
HIGHZ
JTAG Register Definitions
lists the public, usable instructions that are supported along with their encoding.
SMP Required
CMP
HI_Z
BYP Required
EXT
IDC
JTAG Instruction Shift Register
OR
EXTEST Instruction
IDCODE
Required
Optional
Optional
Optional
Optional
Class
IR[3:0]
0000
0001
0010
0011
0100
0111
1000
1111
Select BS register while applying fixed values to output pins and asserting functional
reset
Selects IDCODE register for shift
Selects BS register for shift, sample, and preload without disturbing functional
operation
Selects bypass while applying fixed values to output pins and asserting functional
reset
Selects the bypass register while tri-stating all output pins and asserting functional
reset
User defined function for device test
User defined function for device test
Selects the bypass register for data operations
MCF5253 Reference Manual, Rev. 1
Table 21-2. JTAG Instructions
Instruction Summary
Freescale Semiconductor