MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 109

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

7.3.1.2
The DRAM address and control register (DACR0), shown in
value and the control bits for the memory block of the DRAM controller. Address and timing are also
controlled by bits in DACR0.
Table 7-5
Freescale Semiconductor
Field
RTIM
10–9
31–18
17–16
Field
8–0
Address MBAR+0x108 (DACR0)
RC
11
IS
BA
Reset – – – – – – – – – – – – – – – –
Table 7-5. DRAM Address and Control Register (DACR0) Field Descriptions (Synchronous Mode)
Table 7-4. DRAM Control Register (DCR) Field Descriptions (Synchronous Mode) (continued)
W
R
Initiate self-refresh command.
0 Take no action or issue a
1 If DCR[COC] = 0, the DRAM controller sends a
state where they remain until IS is cleared, at which point the controller sends a
exit self-refresh. The refresh counter is suspended while the SDRAM is in self-refresh; the SDRAM controls the
refresh period.
Refresh timing. Determines the timing operation of auto-refresh in the DRAM controller. Specifically, it determines the
number of clocks inserted between a
in the SDRAM specification.
00 3 clocks
01 6 clocks
1x 9 clocks
Refresh count. Controls refresh frequency. The number of bus clocks between refresh cycles is (RC + 1) * 16. Refresh
can range from 16–8192 bus clocks to accommodate both standard and low-power DRAMs with bus clock operation
from less than 2 MHz to greater than 50 MHz.
The following example calculates RC for an auto-refresh period for 4096 rows to receive 64 mS of refresh every
15.625 µs for each row (625 bus clocks at 40 MHz).
# of bus clocks = 625 = (RC field + 1) * 16
RC = (625 bus clocks/16) -1 = 38.06, which rounds to 38; therefore, RC = 0x26.
Base address register. With DMR[BAM], determines the address range in which the associated DRAM block is
located. Each BA bit is compared with the corresponding address of the current bus cycle. If all unmasked bits match,
the address hits in the associated DRAM block.
Reserved, should be cleared.
describes DACR0 fields.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRAM Address and Control (DACR0) (Synchronous Mode)
Figure 7-4. DRAM Address and Control Register (DACR0) (Synchronous Mode)
BA
SELFX
MCF5253 Reference Manual, Rev. 1
command to exit self refresh.
REF
command and the next possible
SELF
Description
Description
command to the SDRAMv to put it in low-power, self-refresh
RE
15
0
Figure
14 13
–
CASL
–
7-4, contain the base address compare
12 11 10 9 8 7
–
ACTV
– – – – –
Synchronous DRAM Controller Module
command. This corresponds to t
SELFX
CBM
command for the SDRAM to
IMRS PS IP PM
Access: User read/write
0
6
– – –
5 4
3
–
2
RC
– –
1 0
7-5