MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 482

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.6.3.3
The interrupts to the software are enabled with this register. An interrupt is generated when a bit is set and
the corresponding interrupt is active. The USB Status register (USBSTS) still shows interrupt sources even
if they are disabled by the USBINTR register, allowing polling of interrupt events by the software.
24-20
(USBERRINT)
Address MBAR2 0x748
Field
31–9 Reserved.
SLE
(USBINT)
Reset
Reset
8
Field
UEI
UI
W
W
1
0
R
R
Sleep Enable. This is a non-EHCI bit. When this bit is a one, and the DCSuspend bit in the USBSTS register transitions,
the controller will issue an interrupt. The interrupt is acknowledged by the software writing a one to the DCSuspend bit.
Used only in device mode.
1 Enable.
0 Disable.
31
15
0
0
Table 24-16. USB Status Register (USBSTS) Register Field Descriptions (continued)
USB Interrupt Enable Register (USBINTR)
USB Error Interrupt (USBERRINT). When completion of a USB transaction results in an error condition, this bit
is set by the controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred
also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in EHCI for a complete list of host error
interrupt conditions. Also see
controller in device mode, only resume signaling is detected, all others are ignored.
1 Error detected.
0 No error.
USB Interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion of a USB
transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by
the controller when a short packet is detected. A short packet is when the actual number of bytes received was
less than the expected number of bytes.
30
14
Table 24-17. USB Interrupt Enable (USBINTR) Register Field Descriptions
0
0
29
13
0
0
Figure 24-16. USB Interrupt Enable (USBINTR) Register
28
12
0
0
27
11
0
0
MCF5253 Reference Manual, Rev. 1
Table 24-88
26
10
0
0
25
0
0
9
in this chapter for more information on device error matrix. For the
Description
SLE
24
0
0
8
Description
SRE
23
0
0
7
URE
22
0
0
6
AAE
21
0
0
5
SEE
20
0
0
4
FRE
19
0
0
3
Freescale Semiconductor
Access: User read/write
PCE
18
0
0
2
UEE
17
0
0
1
UE
16
0
0
0