MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 372

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
20.1.1
The BKPT active-low input signal is used to request a manual breakpoint. Its assertion causes the processor
to enter a halted state after the completion of the current instruction. The halt status is reflected on the
processor status (PST) pins as the value $F.
20.1.2
These output signals display the hardware register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the
configuration/status register (CSR). Additionally, execution of the WDDATA instruction by the processor
captures operands which are displayed on DDATA. These signals are updated each processor cycle.
20.1.3
This input signal is synchronized internally and provides the clock for the serial communication port to the
debug module. The maximum frequency is 1/5 the speed of the processor’s clock (CLK). At the
synchronized rising edge of DSCLK, the data input on DSI is sampled, and the DSO output changes state.
See
20.1.4
The input signal is synchronized internally and provides the data input for the serial communication port
to the debug module.
20.1.5
This signal provides serial output communication for the debug module responses.
20.1.6
These output signals report the processor status.
outputs indicate the current status of the processor pipeline and are not related to the current bus transfer.
The PST value is updated each processor cycle.
20-2
Figure 20-3
Breakpoint (BKPT)
Debug Data (DDATA[3:0])
Development Serial Clock (DSCLK)
Development Serial Input (DSI)
Development Serial Output (DSO)
Processor Status (PST[3:0])
for more information.
MCF5253 Reference Manual, Rev. 1
Table 20-1
shows the encoding of these signals. These
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