MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 116

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Synchronous DRAM Controller Module
Accesses in synchronous burst page mode always cause the following sequence:
7.4.4
Continuous page mode is identical to burst page mode, except that it allows the processor core to handle
successive bus cycles that hit the same page without having to close the page. When the current bus cycle
finishes, the MCF5253 core internal pipelined bus can predict whether the upcoming cycle will hit in the
same page.
7-12
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
•
•
•
D[31:16]
ACTV
NOP
PALL
If the next bus cycle is not pending or misses in the page, the
SDRAM.
If the next bus cycle is pending and hits in the page, the page is left open, and the next SDRAM
access begins with a
Because of the nature of the internal CPU pipeline this condition does not occur often; however,
the use of continuous page mode is recommended because it can provide a slight performance
increase.
SDRAS
SDCAS
A[31:0]
XDQM
SDWE
SD_CS0
BCLK
Continuous Page Mode
commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
command
command
ACTV
t
CASL
Row
= 2
NOP
READ
READ
Figure 7-7. Burst Write SDRAM Access
or
NOP
or
Column
WRITE
MCF5253 Reference Manual, Rev. 1
WRITE
commands to assure the
commands to service the transfer size with the given port size
command.
Column Column
WRITE
t
RWL
ACTV
NOP
-to-precharge delay
Column
PALL
ACTV
command is generated to the
PALL
delay
t
RP
Freescale Semiconductor
NOP
commands)