MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 107

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Commands are issued to memory using specific encoding on address and control pins. After system reset,
a command must be sent to the SDRAM mode register to configure SDRAM operating parameters.
7.2.1
Table 7-2
Figure 7-2
7.3
The memory map is shown in
Freescale Semiconductor
SD_CS0
SDRAS
SDCAS
BCLKE
Signal
SDWE
UDQM
LDQM
BCLK
SDRAM Memory Map and Register Definitions
shows the behavior of DRAM signals in synchronous mode.
shows a typical signal configuration for synchronous mode.
DRAM Controller Signals in Synchronous Mode
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the
SDRAM. SDRAS should be connected to the corresponding SDRAM SRAS.
Synchronous column address strobe. Indicates a valid column address is present and can be latched by the
SDRAM. SDCAS should be connected to the corresponding signal labeled SCAS on the SDRAM.
DRAM read/write. Asserted for write operations and negated for read operations.
Chip Select for the SDRAM memory block connected to the MCF5253.
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and
disables the clock internal to SDRAM. When BCLKE is low, memory can enter a power-down mode where
operations are suspended or they can enter self-refresh mode. BCLKE functionality is controlled by DCR[COC].
For designs using external multiplexing, setting COC allows BCLKE to provide command-bit functionality.
Column address strobe. For synchronous operation, UDQM, LDQM function as byte enables to the SDRAMs.
They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
Bus clock output. Connects to the CLK input of SDRAMs.
Synchronous operation is selected by setting DCR[SO], DRAM controller
registers reflect the synchronous operation.
MCF5253
Table 7-2. Synchronous DRAM Signal Connections
SD_CS0
Table
U/L DQM
D[31:16]
SDCAS
SDRAS
BCLKE
A[31:0]
SDWE
Figure 7-2. MCF5253 SDRAM Interface
BCLK
7-3. Field and bit descriptions are shown in the following sections.
MCF5253 Reference Manual, Rev. 1
NOTE
Description
CS
ADDRESS
DATA
DQM
WE
CAS
RAS
CKE
CLK
SDRAM
Synchronous DRAM Controller Module
7-3